Saturday, December 18, 2010

Are RISC processors dead, killed by Intel?

What drives the market to settle on an architecture is, almost certainly, the availability of applications; IA-32 (Intel Architecture 32-bit, once known as x86) has clearly benefited from this effect since the introduction of the PC. This architecture, because of its complexity, is not positioned to offer the best performance potential; but its extremely large sales volumes allowed Intel to make substantial investments in research and development (R&D), allowing its processors to match the best RISC processors (except for floating point).

Development of IA-32 has not stopped, and RISC processors will have an increasingly difficult time competing with the architecture for entrylevel and mid-range systems.

With the new IA-64 architecture, Intel squarely faces RISC machines on their own ground—high performance (both integer and floating point) together with 64-bit addressing. Itanium, the first implementation of this architecture, hardly met expectations in terms of integer performance or availability date. Itanium 2 and its successors are likely to remedy this situation. In looking at the situation, recall that IA-64 performance has two interrelated components: compilers, which must extract and express the internal parallelism in programs; and the performance of the processor itself. HP’s contribution, especially for the compiler, is invaluable to Intel, to whom this is a new field.

We should not forget that there is constant progress in IA-32 implementations (and in IA-32 compatibles), a factor that delays the penetration of IA-64, a new architecture lacking the large applications catalogue of IA-32.

Our comment on the Itanium catalogue refers to the IA-64 native catalogue; Intel has provided IA-64 with the ability to execute IA-32 applications, thereby getting Intel the support of the key vendors of applications, databases, middleware, and operating systems—albeit not at the same performance as could be obtained with native Itanium applications.

Because the investment needed to develop new implementations of an architecture keeps growing faster than the market, the tendency will be for the number of RISC architectures to reduce. The survivors will be those with either sufficient market volume, or very strong compatibility reasons. We have already seen a number of RISC architectures fall by the wayside; we can reasonably suppose that just a few years in the future we will see a maximum of two RISC architectures (plus IA-64) surviving. Of course, IA-32 will continue to exist, too.

The real challenge for IA-64 in the area of IA-32 support arises with AMD’s introduction of a straightforward extension of IA-32 to 64-bit architecture, allowing a smooth coexistence and migration between the two architectures. This will be particulary interesting to watch in the next few years.

Source of Information : Elsevier Server Architectures 2005
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